The TLB references physical memory addresses in its table. The TLB may reside between the CPU and the cache, or between the cache and primary storage memory. This depends on whether the cache is using virtual addressing or physical addressing.
If the cache is virtually addressed, requests are sent directly from the CPU to the cache, which then accesses the TLB as necessary. If the cache is physically addressed, the CPU does a TLB lookup on every memory operation, and the resulting physical address is sent to the cache. There are pros and cons to both implementations.